A Pipelined Multi Core Machine With Operating System Support
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A Pipelined Multi-Core Machine with Operating System Support
This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk
PROCEEDINGS OF THE 23RD CONFERENCE ON FORMAL METHODS IN COMPUTER-AIDED DESIGN – FMCAD 2023
Author: Alexander Nadel
language: en
Publisher: TU Wien Academic Press
Release Date: 2023-10-13
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system testing.
A Pipelined Multi-core MIPS Machine
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.