A Pipelined Multi Core Mips Machine


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A Pipelined Multi-core MIPS Machine


A Pipelined Multi-core MIPS Machine

Author: Mikhail Kovalev

language: en

Publisher: Springer

Release Date: 2014-11-24


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This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

A Pipelined Multi-Core Machine with Operating System Support


A Pipelined Multi-Core Machine with Operating System Support

Author: Petro Lutsyk

language: en

Publisher: Springer Nature

Release Date: 2020-05-09


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This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk

SOFSEM 2013: Theory and Practice of Computer Science


SOFSEM 2013: Theory and Practice of Computer Science

Author: Peter van Emde Boas

language: en

Publisher: Springer

Release Date: 2013-01-12


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This book constitutes the refereed proceedings of the 39th International Conference on Current Trends in Theory and Practice of Computer Science, SOFSEM 2013, held in Špindlerův Mlýn, Czech Republic, in January 2013. The 37 revised full papers presented in this volume were carefully reviewed and selected from 98 submissions. The book also contains 10 invited talks, 5 of which are in full-paper length. The contributions are organized in topical sections named: foundations of computer science; software and Web engineering; data, information, and knowledge engineering; and social computing and human factors.