Stochastic Process Variation In Deep Submicron Cmos
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Stochastic Process Variation in Deep-Submicron CMOS
Author: Amir Zjajo
language: en
Publisher: Springer Science & Business Media
Release Date: 2013-11-19
One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
Advancing VLSI through Machine Learning
Author: Abhishek Narayan Tripathi
language: en
Publisher: CRC Press
Release Date: 2025-03-31
This book explores the synergy between very large-scale integration (VLSI) and machine learning (ML) and its applications across various domains. It investigates how ML techniques can enhance the design and testing of VLSI circuits, improve power efficiency, optimize layouts, and enable novel architectures. This book bridges the gap between VLSI and ML, showcasing the potential of this integration in creating innovative electronic systems, advancing computing capabilities, and paving the way for a new era of intelligent devices and technologies. Additionally, it covers how VLSI technologies can accelerate ML algorithms, enabling more efficient and powerful data processing and inference engines. It explores both hardware and software aspects, covering topics like hardware accelerators, custom hardware for specific ML tasks, and ML-driven optimization techniques for chip design and testing. This book will be helpful for academicians, researchers, postgraduate students, and those working in ML-driven VLSI.
Brain-Machine Interface
This book provides a complete overview of significant design challenges in respect to circuit miniaturization and power reduction of the neural recording system, along with circuit topologies, architecture trends, and (post-silicon) circuit optimization algorithms. The introduced novel circuits for signal conditioning, quantization, and classification, as well as system configurations focus on optimized power-per-area performance, from the spatial resolution (i.e. number of channels), feasible wireless data bandwidth and information quality to the delivered power of implantable system.