Quality Driven Systemc Design
Download Quality Driven Systemc Design PDF/ePub or read online books in Mobi eBooks. Click Download or Read Online button to get Quality Driven Systemc Design book now. This website allows unlimited access to, at the time of writing, more than 1.5 million titles, including hundreds of thousands of titles in various foreign languages.
Quality-Driven SystemC Design
Author: Daniel Große
language: en
Publisher: Springer Science & Business Media
Release Date: 2009-12-02
A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.
Models, Methods, and Tools for Complex Chip Design
Author: Jan Haase
language: en
Publisher: Springer Science & Business Media
Release Date: 2013-09-18
This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.
Complete Symbolic Simulation of SystemC Models
In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety properties in (cyclic) finite state spaces, by exhaustive exploration of all possible inputs and process schedulings. The state explosion problem is alleviated by integrating two complementary reduction techniques. Compared to existing approaches, the complete symbolic simulation works more efficiently, and therefore can provide correctness proofs for larger systems, which is one of the most challenging tasks, due to the ever increasing complexity.