Protecting Chips Against Hold Time Violations Due To Variability
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Protecting Chips Against Hold Time Violations Due to Variability
Author: Gustavo Neuberger
language: en
Publisher: Springer Science & Business Media
Release Date: 2013-10-01
With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design. The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability. To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.
Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.
Internet of Things. A Confluence of Many Disciplines
This book constitutes the refereed post-conference proceedings of the Second IFIP International Cross-Domain Conference on Internet of Things, IFIPIoT 2019, held in Tampa, USA, in October/ November 2019. The 11 full papers presented were carefully reviewed and selected from 22 submissions. Also included in this volume are 8 invited papers. The papers are organized in the following topical sections: IoT applications; context reasoning and situational awareness; IoT security; smart and low power IoT; smart network architectures; and smart system design and IoT education.