Open Verification Methodology
Download Open Verification Methodology PDF/ePub or read online books in Mobi eBooks. Click Download or Read Online button to get Open Verification Methodology book now. This website allows unlimited access to, at the time of writing, more than 1.5 million titles, including hundreds of thousands of titles in various foreign languages.
Open Verification Methodology Cookbook
Author: Mark Glasser
language: en
Publisher: Springer Science & Business Media
Release Date: 2009-07-24
Functional verification is an art as much as a science. It requires not only creativity and cunning, but also a clear methodology to approach the problem. The Open Verification Methodology (OVM) is a leading-edge methodology for verifying designs at multiple levels of abstraction. It brings together ideas from electrical, systems, and software engineering to provide a complete methodology for verifying large scale System-on-Chip (SoC) designs. OVM defines an approach for developing testbench architectures so they are modular, configurable, and reusable. This book is designed to help both novice and experienced verification engineers master the OVM through extensive examples. It describes basic verification principles and explains the essentials of transaction-level modeling (TLM). It leads readers from a simple connection of a producer and a consumer through complete self-checking testbenches. It explains construction techniques for building configurable, reusable testbench components and how to use TLM to communicate between them. Elements such as agents and sequences are explained in detail.
TLM-driven Design and Verification Methodology
This book describes a comprehensive SystemC TLM-driven IP design and verification solution'including methodology guidelines, high-level synthesis, and TLM-aware verification basedon Cadence products'that will help designers transition to a TLM-driven design andverification flow.
Verification Methodology Manual for SystemVerilog
Author: Janick Bergeron
language: en
Publisher: Springer Science & Business Media
Release Date: 2005-12-29
Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.