Nergy Efficient Embedded System Design
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System-Level Design Techniques for Energy-Efficient Embedded Systems
System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone.
Energy-Efficient Embedded System Design
The pursuit of energy-efficient design in embedded systems has long become a critical issue. With improved energy effciency, the systems can incorporate more functionality and support better performances. Conventional design techniques innovate in hierarchical design levels from system, algorithm, architecture, to circuit. However, with the slowing of Moore's effect, efforts other than the circuit-level design are becoming more promising for the emerging applications. In this work, we investigate the core signal processing units in wireless communication systems and introduce a suite of new techniques from algorithm to architecture levels to improve energy effciency. First, we develop a comprehensive message truncation scheme to mitigate the decoding complexity of non-binary LDPC decoders. The dynamic channel state is exploited in the initialization stage to reduce message length. We then further prune the messages employing the inter-iteration decoding state of the core computational unit. The arithmetical logic and memory usage could be substantially decreased and therefore reduces the decoder power with the shorter messages. We also propose an adaptive offset correction mechanism to minimize the possible performance loss due to message truncation. And we develop a novel decoder architecture to accommodate the proposed algorithm designs. Second, we introduce a new non-binary LDPC decoder architecture with a low-power memory unit. As non-binary LDPC decoding is memory intensive and more than half of the power is consumed by memory access, the decoder power decreases significantly with the reduced memory power. Although over-scaling in memory power may introduce soft errors, LDPC codes could correct them with the error-resilience as channel codes. To find the extent to scale memory power, we train the decoder with the performance constraint under given channel states before the exploitations. Finally, we investigate the optimal sequential control policy for the signal tracking of GNSS receivers powered by renewable energy. With the proposed greedy and reinforcement learning algorithm, the receiver could opportunistically utilize the harvested energy by jointly considering the signal-noise ratio of the received signal and the available energy level. Different than conventional efforts, we could significantly maximize both energy efficiency and system service time with the desired positioning performances.
Energy Efficient Embedded Video Processing Systems
Author: Muhammad Usman Karim Khan
language: en
Publisher: Springer
Release Date: 2017-09-17
This book provides its readers with the means to implement energy-efficient video systems, by using different optimization approaches at multiple abstraction levels. The authors evaluate the complete video system with a motive to optimize its different software and hardware components in synergy, increase the throughput-per-watt, and address reliability issues. Subsequently, this book provides algorithmic and architectural enhancements, best practices and deployment models for new video systems, while considering new implementation paradigms of hardware accelerators, parallelism for heterogeneous multi- and many-core systems, and systems with long life-cycles. Particular emphasis is given to the current video encoding industry standard H.264/AVC, and one of the latest video encoders (High Efficiency Video Coding, HEVC).