High Performance Parallel Computing Gatech
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Languages and Compilers for Parallel Computing
In 2008 the Workshop on Languages and Compilers for Parallel Computing left the USA to celebrate its 21st anninversary in Edmonton, Alberta, Canada. Following its long-established tradition, the workshop focused on topics at the frontierofresearchanddevelopmentinlanguages,optimizingcompilers,appli- tions, and programming models for high-performance computing. While LCPC continues to focus on parallel computing, the 2008 edition included the pres- tation of papers on program analysis that are precursors of high performance in parallel environments. LCPC 2008 received 35 paper submissions. Eachpaper received at least three independent reviews, and then the papers and the referee comments were d- cussed during a Program Committee meeting. The PC decided to accept 18 papers as regular papers and 6 papers as short papers. The short papers appear at the end of this volume. The LCPC 2008 program was fortunate to include two keynote talks. Keshav Pingali’s talk titled “Amorphous Data Parallelism in Irregular Programs” - gued that irregular programs have data parallelism in the iterative processing of worklists. Pingali described the Galois system developed at The University of Texas at Austin to exploit this kind of amorphous data parallelism. The second keynote talk, “Generic ParallelAlgorithms in Threading Building Bocks (TBB),” presented by Arch Robison from Intel Corporation addressed very practical aspects of using TBB, a production C++ library, for generic p- allel programming and contrasted TBB with the Standard Template Library (STL).
Introduction to High Performance Computing for Scientists and Engineers
Written by high performance computing (HPC) experts, Introduction to High Performance Computing for Scientists and Engineers provides a solid introduction to current mainstream computer architecture, dominant parallel programming models, and useful optimization strategies for scientific HPC. From working in a scientific computing center, the author
Parallel Computer Routing and Communication
This workshop was a continuation of the PCRCW ’94 workshop that focused on issues in parallel communication and routing in support of parallel processing. The workshop series provides a forum for researchers and designers to exchange ideas with respect to challenges and issues in supporting communication for high-performance parallel computing. Within the last few years we have seen the scope of interconnection network technology expand beyond traditional multiprocessor systems to include high-availability clusters and the emerging class of system area networks. New application domains are creating new requirements for interconnection network services, e.g., real-time video, on-line data mining, etc. The emergence of quality-of-service guarantees within these domains challenges existing approaches to interconnection network design. In the recent past we have seen the emphasis on low-latency software layers, the application of multicomputer interconnection technology to distributed shared-memory multiprocessors and LAN interconnects, and the shift toward the use of commodity clusters and standard components. There is a continuing evolution toward powerful and inexpensive network interfaces, and low-cost, high-speed routers and switches from commercial vendors. The goal is to address the above issues in the context of networks of workstations, multicomputers, distributed shared-memory multiprocessors, and traditional tightly-coupled multiprocessor interconnects. The PCRCW ’97 workshop presented 20 regular papers and two short papers covering a range of topics dealing with modern interconnection networks. It was hosted by the Georgia Institute of Technology and sponsored by the Atlanta Chapter of the IEEE Computer Society.