Wideband Discrete Time Delta Sigma Analog To Digital Converters With Shifted Loop Delays

Wideband Discrete-time Delta-sigma Analog-to-digital Converters with Shifted Loop Delays

Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop delays (SLD) technique can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the active adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC. The second project describes two techniques to enhance the noise shaping function in the proposed low-distortion [delta sigma] modulator with shifted loop delays. One is self-noise coupling based on low-distortion [delta sigma] structure; the other is noise-coupled time-interleaved [delta sigma] modulator. Both architectures use shifted loop delays to relax the critical timing constraints in the modulator feedback path, then to save power consumption of each block in the modulators. Two [delta sigma] ADCs were analyzed and simulated in a 0.18 um CMOS technology. The simulation results highly verify the effectiveness of the proposed structure. The third system describes the design technique for double-sampled wideband [delta sigma] ADCs with shifted loop delays (SLD). The added loop delay in the feedback branch relaxes the critical timing for DEM logic. Delay shifting can be combined with such useful techniques as low-distortion circuitry and noise coupling for wideband [delta sigma] modulators. The presented techniques relax the timing for inherent quantization delay, reduce the speed requirements for the critical circuit blocks, and achieve power efficiency by replacing the power-hungry blocks normally used in the modulators. Analysis of all architectures allows the choice of the most power-efficient topology for a wideband [delta sigma] modulator. The proposed second-order and third-order [delta sigma] modulators were designed and simulated to verify the effectiveness of the shifted loop delays techniques.

CMOS Time-Mode Circuits and Systems

Time-mode circuits, where information is represented by time difference between digital events, offer a viable and technology-friendly means to realize mixed-mode circuits and systems in nanometer complementary metal-oxide semiconductor (CMOS) technologies. Various architectures of time-based signal processing and design techniques of CMOS time-mode circuits have emerged; however, an in-depth examination of the principles of time-based signal processing and design techniques of time-mode circuits has not been available—until now. CMOS Time-Mode Circuits and Systems: Fundamentals and Applications is the first book to deliver a comprehensive treatment of CMOS time-mode circuits and systems. Featuring contributions from leading experts, this authoritative text contains a rich collection of literature on time-mode circuits and systems. The book begins by presenting a critical comparison of voltage-mode, current-mode, and time-mode signaling for mixed-mode signal processing and then: Covers the fundamentals of time-mode signal processing, such as voltage-to-time converters, all-digital phase-locked loops, and frequency synthesizers Investigates the performance characteristics, architecture, design techniques, and implementation of time-to-digital converters Discusses time-mode delta-sigma-based analog-to-digital converters, placing a great emphasis on time-mode quantizers Includes a detailed study of ultra-low-power integrated time-mode temperature measurement systems CMOS Time-Mode Circuits and Systems: Fundamentals and Applications provides a valuable reference for circuit design engineers, hardware system engineers, graduate students, and others seeking to master this fast-evolving field.

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