Wafer Scale Integration Iii
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Wafer Scale Integration, III
The purpose of this book is to give an up-to-date presentation of architectures and technologies for wafer-scale integration. As such, it is an overview of the work of the leading research centers active in this area, and an outline of expected evolution and progress in the subject. New technological solutions are envisioned; while the use of optical technologies for interconnections promises to overcome one of the main restrictions to architectures on a wafer, the extension of quick-prototyping solutions to the wafer dimension allows the introduction of wafer-scale systems in educational environments as well as in applications where a quick result and limited production would make traditional silicon solutions unacceptable. Regarding architectures and their applications, three different lines of approach can be identified. Evolutive solutions are proposed, mainly concerning array architectures and restructuring techniques. Innovative architectures are presented, several papers dealing with neural nets. There are also architectures designed not just for experimental reasons but for industrial production. Overall, non-numerical applications predominate.
Wafer Level 3-D ICs Process Technology
Author: Chuan Seng Tan
language: en
Publisher: Springer Science & Business Media
Release Date: 2009-06-29
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Wafer Scale Integration
Author: Earl E. Swartzlander Jr.
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.