Transient Floating Body Effects For Memory Applications In Fully Depleted Soi Mosfets
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Transient Floating-Body Effects for Memory Applications in Fully-Depleted SOI MOSFETs
Author: Maryline Bawedin
language: en
Publisher: Presses univ. de Louvain
Release Date: 2007
Memory devices based on floating-body effects (FBE) in Silicon-on-Insulator (SOI) technology are among the most promising candidates for sub-100nm and low power Dynamic Random Access Memory (DRAM). This new type of DRAMs, called Zero-Capacitor RAM (Z-RAM), uses only one transistor in partially-depleted (PD) SOI technology and takes advantage of FBE which have been considered as parasitic phenomena until now. The Z-RAM programming principles are based on the threshold voltage VTH variations induced by the excess or lack of majority carriers in the floating body. In this dissertation, a new floating-body effect, the Transient Floating Body Potential Effect (TFBPE), based on the body majority carriers non-equilibrium and on the dual dynamic gate coupling in standard fully-depleted (FD) SOI MOSFETs is presented for the first time. The TFBPE occurs in a specific gate bias range and can induce strong hysteresis of the gate and drain current characteristics although the FD SOI transistors are usually known to be immune against the FBE and their aftermaths. Adapted from the same physics principles as in the drain current hysteresis, that we called the Meta-Stable Dip (MSD) effect, a new concept of one-transistor capacitor-less memory was also proposed, the Meta-Stable DRAM (MSDRAM) which is dedicated for double-gate operations. All the experimental results and physics interpretations were supported by 2D numerical simulations. A 1D semi-analytical model of the body potential for non-equilibrium states was also proposed. For the first time, this original body-potential model takes into account the majority carriers density variations, i.e., the quasi-Fermi level non-equilibrium versus a transient gate voltage scan in a FD MOS device.
Low Power VLSI Design
Author: Angsuman Sarkar
language: en
Publisher: Walter de Gruyter GmbH & Co KG
Release Date: 2016-08-08
This book teaches basic and advanced concepts, new methodologies and recent developments in VLSI technology with a focus on low power design. It provides insight on how to use Tanner Spice, Cadence tools, Xilinx tools, VHDL programming and Synopsis to design simple and complex circuits using latest state-of-the art technologies. Emphasis is placed on fundamental transistor circuit-level design concepts.
Floating Body Cell
This book focuses on the technologies of the floating body cell (FBC), which is regarded as the most probable candidate to replace the conventional 1T-1C DRAM. It covers basic principles, procedures for device structure optimization, operational methods, relations between different applications, and their suitable technology options. One of the aut