Trace Based Post Silicon Validation For Vlsi Circuits


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Trace-Based Post-Silicon Validation for VLSI Circuits


Trace-Based Post-Silicon Validation for VLSI Circuits

Author: Xiao Liu

language: en

Publisher: Springer Science & Business Media

Release Date: 2013-06-12


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This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices.

Trace-Based Post-Silicon Validation for VLSI Circuits


Trace-Based Post-Silicon Validation for VLSI Circuits

Author: Xiao Liu

language: en

Publisher:

Release Date: 2013-06-30


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Post-Silicon Validation and Debug


Post-Silicon Validation and Debug

Author: Prabhat Mishra

language: en

Publisher: Springer

Release Date: 2018-09-01


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This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs.