Testing Static Random Access Memories
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Testing Static Random Access Memories
Author: Said Hamdioui
language: en
Publisher: Springer Science & Business Media
Release Date: 2004-03-31
Embedded memories are one of the fastest growing segments oftoday's new technology market. According to the 2001 InternationalTechnology Roadmap for Semiconductors, embedded memories will continueto dominate the increasing system on chip (SoC) content in the nextseveral years, approaching 94% of the SoC area in about 10 years.Furthermore, the shrinking size of manufacturing structures makesmemories more sensitive to defects. Consequently, the memory yieldwill have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requiresunderstanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficientself-test and repair schemes."Testing Static Random Access Memories" covers testing of one ofthe important semiconductor memories types; it address testing ofstatic random access memories (SRAMs), both single-port andmulti-port. It contributes to the technical acknowledge needed bythose involved in memory testing, engineers and researchers. The bookbegins with outlining the most popular SRAMs architectures. Then, thedescription of realistic fault models, based on defect injection andSPICE simulation, are introduced. Thereafter, high quality and lowcost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with somepreliminary test results showing the importance of the new tests inreducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies isalso discussed.Features:
High Performance Memory Testing
Author: R. Dean Adams
language: en
Publisher: Springer Science & Business Media
Release Date: 2005-12-29
Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
Advanced Test Methods for SRAMs
Author: Alberto Bosio
language: en
Publisher: Springer Science & Business Media
Release Date: 2009-10-08
Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.