Systolic Computations
Download Systolic Computations PDF/ePub or read online books in Mobi eBooks. Click Download or Read Online button to get Systolic Computations book now. This website allows unlimited access to, at the time of writing, more than 1.5 million titles, including hundreds of thousands of titles in various foreign languages.
Systolic Computations
Author: M.A. Frumkin
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
This monograph is devoted to a new method of parallel computing which uses VLSI technology in an effcient manner. By this method, data are fed to the cells of a systolic processor and results are obtained instantly. Some theoretical and algorithmic questions which arise in the design of hardware and software for systolic processing are considered. Special attention is devoted to the complexity of VLSI, complexity of algorithms, parallel algorithms, relations between graphs of algorithms and graphs of processors, parallel programming languages, and the use of systolic algorithms for vector programming. The book is unique for its inclusion of a library of systolic algorithms for solving problems from twelve branches of computer science, and will be useful for designers of hardware and software for parallel processing.
Matrix Computations on Systolic-Type Arrays
Author: Jaime Moreno
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage. Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives. Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer.
Concurrent Computations
Author: Stuart K. Tewksbury
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
The 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation was organized as an interdisciplinary work shop emphasizing current research directions toward concurrent computing systems. With participants from several different fields of specialization, the workshop cov ered a wide variety of topics, though by no means a complete cross section of issues in this rapidly moving field. The papers included in this book were prepared for the workshop and, taken together, provide a view of the broad range of issues and alternative directions being explored. To organize the various papers, the book has been divided into five parts. Part I considers new technology directions. Part II emphasizes underlying theoretical issues. Communication issues, which are ad dressed in the majority of papers, are specifically highlighted in Part III. Part IV includes papers stressing the fault tolerance and reliability of systems. Finally, Part V includes systems-oriented papers, where the system ranges from VLSI circuits through powerful parallel computers. Much of the initial planning of the workshop was completed through an informal AT&T Bell Laboratories group consisting of Mehdi Hatamian, Vijay Kumar, Adri aan Ligtenberg, Sailesh Rao, P. Subrahmanyam and myself. We are grateful to Stuart Schwartz, both for the support of Princeton University and for his orga nizing local arrangements for the workshop, and to the members of the organizing committee, whose recommendations for participants and discussion topics were par ticularly helpful. A. Rosenberg, and A. T.