Systematic Modeling And Analysis Of Telecom Frontends And Their Building Blocks
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Systematic Modeling and Analysis of Telecom Frontends and their Building Blocks
Author: Piet Vanassche
language: en
Publisher: Springer Science & Business Media
Release Date: 2005-09-01
To meet the demands of today's highly competitive market, analog electronics designers must develop their IC designs in a minimum of time. The difference between first- and second-time right seriously affects a company’s share of the market. Analog designers are therefore in need for structured design methods together with the theory and tools to support them, especially when pushing the performance limits in high-performance designs. Systematic Modeling and Analysis of Telecom Frontends and Their Building Blocks aims to help designers in speeding up telecommunication frontend design by offering an in-depth understanding of the frontend's behavior together with methods and algorithms that support designers in bringing this understanding to practice. The book treats topics such as time-varying phase-locked loop stability, noise in mixing circuits, oscillator injection locking, oscillator phase noise behavior, harmonic oscillator dynamics and many more. In doing so, it always starts from a theoretical foundation that is both rigorous and general. Phase-locked loop and mixer analysis, for example, are grounded upon a general framework for time-varying small-signal analysis. Likewise, analysis of harmonic oscillator transient behavior and oscillator phase noise analysis are treated as particular applications of a general framework for oscillator perturbation analysis. In order to make the book as easy to read as possible, all theory is always accompanied by numerous examples and easy-to-catch intuitive explanations. As such, the book is suited for both computer-aided design engineers looking for general theories and methods, either as background material or for practical implementation in tools, as well as for practicing circuit designers looking for help and insight in dealing with a particular application or a particular high-performance design problem.
Design of Very High-Frequency Multirate Switched-Capacitor Circuits
Author: Seng-Pan U
language: en
Publisher: Springer Science & Business Media
Release Date: 2006
Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
High-Speed Photodiodes in Standard CMOS Technology
Author: Sasa Radovanovic
language: en
Publisher: Springer Science & Business Media
Release Date: 2006-10-11
High-speed Photodiodes in Standard CMOS Technology describes high-speed photodiodes in standard CMOS technology which allow monolithic integration of optical receivers for short-haul communication. For short haul communication the cost aspect is important , and therefore it is desirable that the optical receiver can be integrated in the same CMOS technology as the rest of the system. If this is possible then ultimately a singe-chip system including optical inputs becomes feasible, eliminating EMC and crosstalk problems, while data rate can be extremely high. The problem of photodiodes in standard CMOS technology it that they have very limited bandwidth, allowing data rates up to only 50Mbit per second. High-speed Photodiodes in Standard CMOS Technology first analyzes the photodiode behaviour and compares existing solutions to enhance the speed. After this, the book introduces a new and robust electronic equalizer technique that makes data rates of 3Gb/s possible, without changing the manufacturing technology. The application of this technique can be found in short haul fibre communication, optical printed circuit boards, but also photodiodes for laser disks.