Systematic Design Of Analog Ip Blocks
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Systematic Design of Analog IP Blocks
Author: Jan Vandenbussche
language: en
Publisher: Springer Science & Business Media
Release Date: 2013-03-14
Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly.
Systematic Design of Sigma-Delta Analog-to-Digital Converters
Author: Ovidiu Bajdechi
language: en
Publisher: Springer Science & Business Media
Release Date: 2004-04-30
Systematic Design of Sigma-Delta Analog-to-Digital Converters describes the issues related to the sigma-delta analog-to-digital converters (ADCs) design in a systematic manner: from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors, capacitors, and amplifier transconductances used in individual integrators. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored range from simple single loops to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components are calculated and the power consumption is estimated, based on top-level requirements like harmonic distortion and noise budget. This unified, systematic approach to choosing the best sigma-delta ADC implementation for a given design target yields an interesting solution for a high-resolution, broadband (DSL-like) ADC operated at low oversampling ratio, which is detailed down to transistor-level schematics. The target audience of Systematic Design of Sigma-Delta Analog-to-Digital Converters are engineers designing sigma-delta ADCs and/or switched-capacitor and continuous-time filters, both beginners and experienced. It is also intended for students/academics involved in sigma-delta and analog CAD research.
Design of Very High-Frequency Multirate Switched-Capacitor Circuits
Author: Seng-Pan U
language: en
Publisher: Springer Science & Business Media
Release Date: 2006
Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.