Studies On Selected Topics In Radio Frequency Digital To Analog Converters
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Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters
Author: Mohammad Reza Sadeghifar
language: en
Publisher: Linköping University Electronic Press
Release Date: 2019-10-14
The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base-stations that can be vastly deployed. That is, while the electrical specification of a radio base-station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network. As the number of antenna elements increases in massive multiple-input multiple-output based radios such as in 5G, designing true multi-band base-station radios, with efficient physical size, power consumption and cost in emerging cellular bands especially in mid-bands (frequencies up to 10~GHz), is becoming a challenge. This demands a hard integration of radio components; particularly the radio's digital application-specific integrated circuits (ASIC) with high-performance energy-efficient multi-band data converters. In this dissertation radio frequency digital-to-analog converter (RF DAC) and semi-digital finite-impulse response (FIR) filter digital-to-analog converter has been studied. Different techniques are used in these structures to improve the transmitter's overall performance. In the RF DAC part, a radio frequency digital-to-analog converter solution is presented, which is capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture, while fulfills the stringent requirements of cellular network radio base station linearity and bandwidth. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone and hence achieving output frequencies up to the sample rate. In the semi-digital FIR part, optimization problem formulation for semi-digital FIR digital-to-analog converter is investigated. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital Sigma-Delta modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in semi-digital FIR DAC optimization problem formulation. It is shown that hardware cost of the semi-digital FIR DAC, can be reduced by introducing flexible coefficient precision in filter optimization while the semi-digital FIR DAC is not over-designed either. Different use cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metric are used in different use cases of the optimization problem formulation and solved to find out the optimum set of analog FIR taps. Moreover, a direct digital-to-RF converter (DRFC) is presented in this thesis where a semi-digital FIR topology utilizes voltage-mode RF DAC cells to synthesize spectrally clean signals at RF frequencies. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital Sigma-Delta modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter. The RF output frequencies are synthesized by a configurable voltage-mode RF DAC solution with a high linearity performance. A compensation technique to cancel the code-dependent supply current variation in voltage-mode RF DAC for radio frequency direct digital frequency synthesizer is also presented in this dissertation and is studied analytically. The voltage-mode RF DAC and the compensation technique are mathematically modeled and system-level simulation is performed to support the analytical discussion.
Energy-Efficient Implementation of Communication Algorithms through Complexity Reduction
Author: Narges Mohammadi Sarband
language: en
Publisher: Linköping University Electronic Press
Release Date: 2024-12-13
Energy-efficient implementations are essential for the future and modern society, especially in digital signal processing (DSP) and communication systems, where the rapid growth of devices, such as those battery-driven internet of things (IoT) sensors, necessitates low-complexity and low-power solutions. This thesis concentrates on two areas: constant multiplication and active user detection in wire-less networks. Constant multiplication can be implemented using a shift-and-add (SHA) network. Typically, the number of adders/subtracters is minimized, but the number of cascaded adders/subtracters (depth) also impacts the power consumption. The two classes of algorithms used to solve the problem are adder graph algorithms or sub-expression sharing algorithms. Adder graph algorithms typically yield better results for a single or a low number of inputs, since they do not depend on the representation of the numbers involved. However, they can lead to very high run times and worse results when the number of inputs is high. At the same time, it is known that it is possible to transpose the problem. For example, a sum of products (many inputs) can be transposed to a single input with multiple coefficients, meaning that it is possible to transpose the problem to the more advantageous form, solve it and then transpose the solution back. However, there has been no systematic algorithm available to obtain the transposed result that takes depth into account. In this thesis, a systematic algorithm that obtains the minimum depth of the transposed SHA network subject to the input is introduced. The practical application of the constant multiplication problem is demonstrated through the implementation of a reconfigurable lowpass equalizer, widely used in communication systems and DSP. Various formulations of the constant multiplication problem, combined with pipelining, are explored to identify the most efficient implementation in a 28 nm FD-SOI standard cell, significantly reducing power consumption and highlighting the real-world impact of our research. The second research focuses on the challenge of detecting active users in massive machine-type communication (mMTC) scenarios involving large numbers of devices. The problem is addressed using a pilot-hopping sequence method and is formulated as a non-negative least-squares (NNLS) problem. This work implements two NNLS algorithms, fast projected gradient (Fast) and multiplicative updates (Mult), to solve the active user detection problem. These implementations are implemented in a 28 nm FD-SOI process and are optimized for energy efficiency, chip area, and detection speed. The results demonstrate the ability to perform over a million detections per second with significantly lower energy consumption compared to existing methods. However, the implementations lack reconfigurability, and it can be argued whether the high detection rates are relevant for current practical applications. To enhance practicality and reconfigurability, the Fast algorithm is implemented using a reconfigurable time-multiplexed architecture, reducing resources by reusing them within one iteration. This architecture employs a novel user re-ordering method to enable parallel memory access and continuous operation for successive iterations, thereby increasing the execution speed. The architecture is implemented on numerous FPGA families, demonstrating resource efficiency and reconfigurability by storing the pilot-hopping sequences in memory, while obtaining a more practically usable detection rate of about one to a few thousand detections per second depending on the FPGA family. Energieffektiva implementationer är avgörande för framtiden och det moderna samhället, särskilt inom digital signalbehandling (DSP) och kommunikationssystem, där den snabba tillväxten av enheter, såsom de inom Internet of Things (IoT), kräver lösningar med låg komplexitet och låg effektförbrukning. Denna avhandling fokuserar på två områden: konstantmultiplikation och detektering av aktiva användare i trådlösa nätverk. Konstantmultiplikation kan implementeras med ett shift-and-add (SHA) nätverk. Vanligtvis så minimeras antalet adderare/subtraherare, men antalet kaskadkopplade adderare/subtraherare (djupet) påverkar också effektförbrukningen. De två klasserna av algoritmer för att lösa konstaktmultiplikation baseras på adderargrafer eller gemensamma deluttryck. Addergrafer är oftast bättre vid en eller få ingångar, eftersom de inte beror på vilken representation som talen uttrycks med. För många ingångar så kan beräkningstiden öka väldigt snabbt samt att resultaten ofta är sämre eftersom sökrymden ökar fort. Samtidigt så är det välkänt att det får att transponera problemet. Till exempel så kan en summa produkter (många ingångar) transponeras till en ingång som multipliceras med många olika konstanter. Detta leder till att det är möjligt att transponera problemet till den mest fördelaktiga formen, lösa det och sedan transponera lösningen. Det har tidigare inte funnits någon systematisk algoritm för att transponera ett nätverk som tar hänsyn till djupet, men i denna avhandling så presenteras en som garanterar minimalt djup givet en viss adderargraf som argument. Den praktiska tillämpningen av konstantmultiplikation demonstreras genom implementering av en konfigurerbar lågpassutjämnare, som är allmänt använd i DSP- och kommunikationssystem. Olika formuleringar av konstantmultiplikationsproblemet, kombinerat med pipelining, utforskas för att identifiera den mest effektiva implementationen i en 28 nm FD-SOI-standardcell, vilket avsevärt minskar strömförbrukningen och visar den verkliga påverkan av vår forskning. Den andra forskningen fokuserar på utmaningen att detektera aktiva användare i massive machinetype communication (mMTC) med ett stort antal enheter. Problemet hanteras med hjälp av en pilothoppingssekvensmetod och formuleras som ett problem med non-negative least-squares (NNLS). Detta arbete implementerar två NNLS-algoritmer, fast projected gradient (Fast) och multiplikativa uppdateringar (Mult), för att lösa problemet med detektering av aktiva användare. Dessa implementationer implementerade i en 28 nm FD-SOI-process och är optimerade för energieffektivitet, chiparea och detekteringshastighet. Resultaten visar att mer än en miljon detektioner per sekund kan utföras med betydligt lägre energiförbrukning än befintliga metoder, till stor del för att en iteration beräknas helt parallelt. Dock saknas möjlighet att ändra användarsekvenser och det kan diskuteras om den höga detektionstakten är praktiskt användbar. För att öka praktiskheten implementeras Fast-algoritmen med en konfigurerbar tidsmultiplexad arkitektur, vilken sparar resurser genom att återanvända dem i en iteration. Denna arkitektur använder en ny metod att ordna om användarna för att möjliggöra parallell minnesåtkomst och kontinuerliga beräkning-ar för efterföljande iterationer, vilket ökar exekveringshastigheten. Arkitekturen implementeras på olika FPGA-familjer och visar resurseffektivitet och konfigurerbarhet genom att pilothoppningssekvenserna sparas i minne, samtidigt som en mer praktiskt användbar detektionshastighet från ungefär ett tusen till några tusen detektioner per sekund beroende på FPGA-familj.
Direct Conversion Receivers in Wide-Band Systems
Author: Aarno Pärssinen
language: en
Publisher: Springer Science & Business Media
Release Date: 2006-04-18
This book is based on my doctoral thesis at the Helsinki University of Technology. Several different projects during five years guided me from the basics of the RF IC design to the implementations of highly integrated radio receiver chips. Sharing time and effort between IC and system issues is not always straightforward. I have been lucky to follow both topics and share experiences with diligent and enthusiastic people having different specialities. As a result, this book will cover a wide range of different topics needed in the design of highly integrated radio receivers. Experiences from the first receiver prototypes for the third generation cellular systems form the basis of this book. Most of the issues are directly related to the early proposals of European and Japanese standardization organizations. For example, the chip rate was originally set to 4. 096 Mcps in a wide-band CDMA channel. I have kept that number in the book in most of the examples although it has been later changed to 3. 84 Mcps. I hope that the readers will accept that and the possible other incompabilities to the latest specifications. At least in the research phase the changes even in the most essential requirements are definitely not a rare incident and IC designers should be able to react and modify their designs as soon as they can.