Single Precision Floating Point Multiplier

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Single Precision Floating Point Multiplier

Author: B. Vinoth Kumar
language: en
Publisher: Anchor Academic Publishing
Release Date: 2017-07
The Floating Point Multiplier is a wide variety for increasing accuracy, high speed and high performance in reducing delay, area and power consumption. The floating point is used for algorithms of Digital Signal Processing and Graphics. Many floating point multipliers are used to reduce the area that perform in both the single precision and the double precision in multiplication, addition and subtraction. Here, the scientific notations sign bit, mantissa and exponent are used. The real numbers are divided into two components: fixed component of significant range (lack of dynamic range) and exponential component in floating point (largest dynamic range). The authors convert decimal to floating point and normalize the exponent part and rounding operation to reduce latency. The mantissa of two values are multiplied and the exponent part is added. The sign results with exclusive-or are obtained. Then, the final result of shift and add floating point multiplier is compared with booth multiplication.
Single Precision Floating Point Multiplier

Author: B. Vinoth Kumar
language: en
Publisher: Anchor Academic Publishing
Release Date: 2017-06-12
The Floating Point Multiplier is a wide variety for increasing accuracy, high speed and high performance in reducing delay, area and power consumption. The floating point is used for algorithms of Digital Signal Processing and Graphics. Many floating point multipliers are used to reduce the area that perform in both the single precision and the double precision in multiplication, addition and subtraction. Here, the scientific notations sign bit, mantissa and exponent are used. The real numbers are divided into two components: fixed component of significant range (lack of dynamic range) and exponential component in floating point (largest dynamic range). The authors convert decimal to floating point and normalize the exponent part and rounding operation to reduce latency. The mantissa of two values are multiplied and the exponent part is added. The sign results with exclusive-or are obtained. Then, the final result of shift and add floating point multiplier is compared with booth multiplication.