Simultaneous Placement And Timing Optimization Using Buffer Insertion Cell Replication And Gate Sizing

Simultaneous Placement and Timing Optimization Using Buffer Insertion, Cell Replication and Gate Sizing

Since the introduction of deep sub-micron technologies, meeting timing specifications have become more difficult. Interconnect delay is now a dominant factor in the total circuit delay as die sizes become larger and device delays decrease. With the larger die sizes interconnects are becoming longer and are a direct factor in determining the overall system performance. In the current practice placement and delay optimization are separated. This separation between placement, and timing optimizations is no longer desirable. Due to the over constrained stages of separate steps it is hard to optimize the final solution. To globally optimize the circuit these existing physical design stages must be combined. An algorithm that runs timing analysis, and optimization during the placement phase is demonstrated in this thesis. Unlike existing methods our timing driven standard-cell placement algorithm is capable of performing buffer insertion, gate sizing, and cell replication entirely during the placement phase. This allows the built-in optimization algorithm to modify net information along with physical cell locations. The primary contribution of this thesis is the integration and algorithm used for performing netlist modifications in the placement phase. Other contributions consist of bin localization, discussed in the force directed placement approach to reduce run time, and the methods for optimization selection. From experimental results it has been shown that with integrated optimization placement can achieve a better delay value when compared with timing driven placement alone.

Commencement

Functional Design Error Diagnosis, Correction and Layout Repair of Digital Circuits