Sequential Optimization Of Asynchronous And Synchronous Finite State Machines

Sequential Optimization of Asynchronous and Synchronous Finite-State Machines

Asynchronous, or unclocked, digital systems have several potential advantages over their synchronous counterparts. In particular, they address a number of challenging problems faced by the designers of large-scale synchronous digital systems: power consumption, worst-case timing constraints, and engineering and design reuse issues associated with the use of a fixed-rate global clock. Moreover, while for synchronous systems these problems are exacerbated by increasing system size, asynchronous systems promise to scale more gracefully. Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools makes three contributions to the field of sequential optimization for finite-state machines: 1) it introduces several new provably-optimal algorithms for the synthesis and optimization of asynchronous finite-state machines (FSMs); 2) it presents practical software implementations of each of these algorithms; and 3) it introduces a complete new CAD package, called MINIMALIST, binding these tools into a state-of-the-art technology-independent synthesis path for `burst-mode' asynchronous circuits. Throughout this book, real-world industrial designs are used as benchmark circuits to validate the usefulness of the tools. As an additional benefit, some of the theory and tools also provide new methods for the optimization of synchronous FSMs.

Sequential Optimization of Asynchronous and Synchronous Finite-state Machines

Design Automation of Real-Life Asynchronous Devices and Systems

The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.