Rf Frontend Design For Process Variation Tolerant Receivers
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RF-Frontend Design for Process-Variation-Tolerant Receivers
Author: Pooyan Sakian
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-02-18
This book discusses wireless receiver design challenges, given the shrinking of circuitry into ever-smaller sizes and resulting complications on manufacturability, production yield and end price of the products. Includes countermeasures for RF designers.
Low-Power Variation-Tolerant Design in Nanometer Silicon
Author: Swarup Bhunia
language: en
Publisher: Springer Science & Business Media
Release Date: 2010-11-10
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
Toward 5G Software Defined Radio Receiver Front-Ends
This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion architecture. This allows readers give a power consumption budget to determine how much filtering is required on the receive path, by considering the ADC performance characteristics and the corresponding blocker diagram.