Reliable And High Performance Hardware Architectures For The Advanced Encryption Standard Galois Counter Mode
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Reliable and High-performance Hardware Architectures for the Advanced Encryption Standard/galois Counter Mode
The high level of security and the fast hardware and software implementations of the Advanced Encryption Standard (AES) have made it the first choice for many critical applications. Since its acceptance as the adopted symmetric-key algorithm, the AES has been utilized in various security-constrained applications, many of which are power and resource constrained and require reliable and efficient hardware implementations. In this thesis, first, we investigate the AES algorithm from the concurrent fault detection point of view. We note that in addition to the efficiency requirements of the AES, it must be reliable against transient and permanent internal faults or malicious faults aiming at revealing the secret key. This reliability analysis and proposing efficient and effective fault detection schemes are essential because fault attacks have become a serious concern in cryptographic applications. Therefore, we propose, design, and implement various novel concurrent fault detection schemes for different AES hardware architectures. These include different structure-dependent and independent approaches for detecting single and multiple stuck-at faults using single and multi-bit signatures. The recently standardized authentication mode of the AES, i.e., Galois/Counter Mode (GCM), is also considered in this thesis. We propose efficient architectures for the AESGCM algorithm. In this regard, we investigate the AES algorithm and we propose lowcomplexity and low-power hardware implementations for it, emphasizing on its nonlinear transformation, i.e., SubByes (S-boxes). We present new formulations for this transformation and through exhaustive hardware implementations, we show that the proposed architectures outperform their counterparts in terms of efficiency. Moreover, we present parallel, high-performance new schemes for the hardware implementations of the GCM to improve its throughput and reduce its latency. The performance of the proposed efficient architectures for the AES-GCM and their fault detection approaches are benchmarked using application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) hardware platforms. Our comparison results show that the proposed hardware architectures outperform their existing counterparts in terms of efficiency and fault detection capability.
Proceedings of International Conference on Data, Electronics and Computing
This book features high-quality, peer-reviewed research papers presented at the International Conference on Data Electronics and Computing (ICDEC 2023) organized by Department of Computer Science & Engineering, Mizoram University (A Central University) Aizawl, India & Department of Computer Science & Engineering, National Institute of Technology Mizoram Aizawl, India during 15 – 16 December 2023. The book covers topics in communication, networking and security, image, video and signal processing; cloud computing, IoT and smart city, AI/ML, big data and data mining, VLSI design, antenna, and microwave and control.
Reconfigurable Computing: Architectures, Tools and Applications
This book constitutes the refereed proceedings of the 5th International Workshop on Applied Reconfigurable Computing, ARC 2009, held in Karlsruhe, Germany, in March 2009. The 21 full papers and 21 short papers presented together with the abstracts of 3 keynote lectures were carefully reviewed and selected from about 100 submissions. The papers are organized in topical sections on FPGA security and bitstream analysis, fault tolerant systems, architectures, place and route techniques, cryptography, and resource allocation and scheduling, as well as on applications.