Principles Of Functional Verification
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Principles of Functional Verification
As design complexity in chips and devices continues to rise, so, too, does the demand for functional verification. Principles of Functional Verification is a hands-on, practical text that will help train professionals in the field of engineering on the methodology and approaches to verification.In practice, the architectural intent of a device is necessarily abstract. The implementation process, however, must define the detailed mechanisms to achieve the architectural goals. Based on a decade of experience, Principles of Functional Verification intends to pinpoint the issues, provide strategies to solve the issues, and present practical applications for narrowing the gap between architectural intent and implementation. The book is divided into three parts, each building upon the chapters within the previous part. Part One addresses why functional verification is necessary, its definition and goals. In Part Two, the heart of the methodology and approaches to solving verification issues are examined. Each chapter in this part ends with exercises to apply what was discussed in the chapter. Part Three looks at practical applications, discussing project planning, resource requirements, and costs. Each chapter throughout all three parts will open with Key Objectives, focal points the reader can expect to review in the chapter.* Takes a "holistic" approach to verification issues* Approach is not restricted to one language* Discussed the verification process, not just how to use the verification language
Effective Functional Verification
Author: Srivatsa Vasudevan
language: en
Publisher: Springer Science & Business Media
Release Date: 2006-07-29
Effective Functional Verification is organized into 4 parts. The first part contains 3 chapters designed appeal to newcomers and experienced people to the field. There is a survey of various verification methodologies and a discussion of them. The second part with 3 chapters is targeted towards people in management and higher up on the experience ladders. New verification engineers reading these chapters learn what is expected and how things work in verification. Some case studies are also presented with analysis of proposed improvements. The last two parts are the result of experience of several years. It goes into how to optimize a verification plan and an environment and how to get results effectively. Various subjects are discussed here to get the most out of a verification environment. Lastely, the appendix discusses some tool specifics to help remove repetitive work and also some tool specific guidelines. While reading Effective Functional Verification, one will be able to get a jump start on planning and executing a verification plan using the concepts presented.
Principles of Verifiable RTL Design
Author: Lionel Bening
language: en
Publisher: Springer Science & Business Media
Release Date: 2001-05-31
The first edition of Principles of Verifiable RTL Design offered a common sense method for simplifying and unifying assertion specification by creating a set of predefined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative, known as the Open Verification Library Initiative (www.verificationlib.org), provides an assertion interface standard that enables the design engineer to capture many interesting properties of the design and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). Furthermore, this standard enables the design engineer to `specify once,' then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that will benefit design and verification engineers while providing unity to the EDA community (e.g., providers of testbench generation tools, traditional simulators, commercial assertion checking support tools, symbolic simulation, and semi-formal and formal verification tools). The second edition of Principles of Verifiable RTL Design expands the discussion of assertion specification by including a new chapter entitled `Coverage, Events and Assertions'. All assertions exampled are aligned with the Open Verification Library Initiative proposed standard. Furthermore, the second edition provides expanded discussions on the following topics: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL (unambiguous mapping to gates); more `bad stuff'. The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, A Functional Coding Style Supporting Verification Processes, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.