Power Management Techniques For Integrated Circuit Design
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Power Management Techniques for Integrated Circuit Design
This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors’ manuals, and program downloads
Power Management Techniques for Integrated Circuit Design
This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors’ manuals, and program downloads
Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
Author: Stephan Henzler
language: en
Publisher: Springer Science & Business Media
Release Date: 2006-11-24
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.