Placement Optimization For Modern Circuit Designs

Modern Circuit Placement

Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization. This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs. Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.

Placement Optimization for Modern Circuit Designs

Routing Congestion in VLSI Circuits

With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow.