Pipelined Ieee 754 Double Precision Floating Point Arithmetic Operators On Virtex Fpga S
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Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA's
Analog and mixed-signal circuit simulation often employs the use of the so-called LU decomposition method to solve a set of linear algebraic equations represented as Ax=b, where A is a square matrix. The LU method requires the factorization of A into two tri-diagonal matrices. Factorization is of order n power 3' time and dominates the execution time of the LU decomposition method. A number of approaches have been developed for reducing the execution time of LU factorization. One approach is to unroll the factorization algorithm and, considering each resulting assignment statement to be a machine operation, interpret the instruction stream. If an interpreter is implemented in a special purpose hardware engine there may be efficiencies to be gained by using a uniquely-developed floating-point unit within the hardware interpreter. This thesis documents the research in exploring alternatives in the design of a special purpose double precision floating point unit for a hardware interpreter to perform LU factorization using unrolled code. Alternatives explored were primarily looking at integer adder and multiplier units of the floating-point unit to determine the speed and area for each integer unit that were considered. A floating-point divider algorithm was also explored and studied. The result of this study for the pipelined floating-point unit gives the best performance with the Block Carry-look-ahead integer adder, Booth-2 integer multiplier and the SRT integer divider units. One of the interesting aspects of this research was heavy use of rapid prototyping. All models were implemented in VHDL to evaluate system level performance, synthesized by Synopsys to gate level, and analyzed for time and area at the logic level. Finally, chip level area and space characteristics were obtained using Xilinx place and route tools.
Reconfigurable Computing: Architectures, Tools and Applications
Author: Oliver Choy
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-03-02
This book constitutes the refereed proceedings of the 8th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2012, held in Hongkong, China, in March 2012. The 35 revised papers presented, consisting of 25 full papers and 10 poster papers were carefully reviewed and selected from 44 submissions. The topics covered are applied RC design methods and tools, applied RC architectures, applied RC applications and critical issues in applied RC.
Reconfigurable Computing
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design— the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardware and software computing to provide an introduction to the entire range of issues relating to reconfigurable computing. FPGAs (field programmable gate arrays) act as the "computing vehicles to implement this powerful technology. Readers will be guided into adopting a completely new way of handling existing design concerns and be able to make use of the vast opportunities possible with reconfigurable logic in this rapidly evolving field. - Designed for both hardware and software programmers - Views of reconfigurable programming beyond standard programming languages - Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways