Pipelined Adaptive Digital Filters

Pipelined Adaptive Digital Filters

Adaptive filtering is commonly used in many communication applications including speech and video predictive coding, mobile radio, ISDN subscriber loops, and multimedia systems. Existing adaptive filtering topologies are non-concurrent and cannot be pipelined. Pipelined Adaptive Digital Filters presents new pipelined topologies which are useful in reducing area and power and in increasing speed. If the adaptive filter portion of a system suffers from a power-speed-area bottleneck, a solution is provided. Pipelined Adaptive Digital Filters is required reading for all users of adaptive digital filtering algorithms. Algorithm, application and integrated circuit chip designers can learn how their algorithms can be tailored and implemented with lower area and power consumption and with higher speed. The relaxed look-ahead techniques are used to design families of new topologies for many adaptive filtering applications including least mean square and lattice adaptive filters, adaptive differential pulse code modulation coders, adaptive differential vector quantizers, adaptive decision feedback equalizers and adaptive Kalman filters. Those who use adaptive filtering in communications, signal and image processing algorithms can learn the basis of relaxed look-ahead pipelining and can use their own relaxations to design pipelined topologies suitable for their applications. Pipelined Adaptive Digital Filters is especially useful to designers of communications, speech, and video applications who deal with adaptive filtering, those involved with design of modems, wireless systems, subscriber loops, beam formers, and system identification applications. This book can also be used as a text for advanced courses on the topic.

Design of Pipelined VLSI Adaptive Digital Filters with Relaxed Look-ahead

Digital Signal Processing with Field Programmable Gate Arrays

Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 30 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, and advanced algorithms with high future potential. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Baseline" software. This edition has a new chapter on adaptive filters, new sections on division and floating point arithmetics, an up-date to the current Altera software, and some new exercises.