Physical Design Of Cmos Integrated Circuits Using L Edit Pdf

Physical Design of CMOS Integrated Circuits Using L-Edit

"Physical Design of CMOS Integrated Circuits Using L-Edit is the first book/software package that enables engineering students and professionals to perform full IC layout on an inexpensive personal computer. The Student Version of L-Edit, included with the book on a 3.5-inch disk, is a full-featured layout editor that runs on MS-DOS compatible computers with minimal hardware requirements (640K RAM, a mouse, and an EGA or better color monitor). L-Edit allows the user to implement the physical design of an integrated circuit at the silicon level, and provides output for circuit simulation on SPICE. The entire process of chip design - once the exclusive province of workstation-based CAD systems - can now be performed on a PC." "Database files for many standard MOSIS CMOS processes are provided on disk, including Orbit and HP 2.0 and 1.2-micron technology base definitions. The program provides for circuit extraction (translating the layout to a SPICE-compatible text file), and design rule checking using predefined MOSIS rules or custom-designed sets. It also features a unique cross-sectional viewer that constructs the side view layering from the layoutthis viewer helps users visualize the link between layout drawings and the device structure. Circuit designs created on the Student Version of L-Edit can be translated to GDS II or CIF format for submission to a fabrication foundry using the Professional Version of L-Edit."--BOOK JACKET.Title Summary field provided by Blackwell North America, Inc. All Rights Reserved

Phys Des Of Cmos Integr Circ

Closing the Gap Between ASIC & Custom

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy’s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.