Multi Configuration Simulation Algorithms For The Evaluation Of Computer Architecture Designs
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Multi-configuration Simulation Algorithms for the Evaluation of Computer Architecture Designs
Abstract: "In computer architecture design, a number of candidate design are simulated on representative workloads, and the most satisfactory design in terms of cost and performance is chosen. This simulation process is time-consuming, especially memory hierarchy simulation, and is a bottleneck in architectural design. In this thesis the multi-configuration simulation approach is adopted for speeding up the simulation process. This approach is based on the observation that the behavior of adjacent design configurations is largely similar, and that the similarity may be exploited to reduce simulation work; significant reductions in simulation time are obtained by a synergistic simulation of many design configurations. A suite of multi-configuration simulation algorithms is developed for memory hierarchy simulation. The suite includes 1. An algorithm for set-associative cache simulation based on a new data structure (the generalized binomial tree) which runs about two times faster than earlier algorithms. 2. An algorithm for direct mapped cache simulation based on a novel tag inclusion property which also gives a factor of two improvement over an earlier algorithm. 3. An innovative limited lookahead algorithm with stack repair for simulating the OPT replacement strategy in caches. 4. Novel multi-configuration simulation algorithms for write-buffers. A simulation package, Cheetah, based on these algorithms has been developed and used in the following modeling and optimization studies. First, a new model, the OPT model, is introduced for classifying cache misses. Unlike earlier models, the OPT model accounts for misses resulting from sub-optimal replacement policies used in practical caches. Experimental characterizations based on the OPT model of the cache misses occurring in the SPEC benchmarks are then presented. The results demonstrate that the replacement policy contributes to a significant fraction of cache misses. Second, the hit-miss and reuse behavior of individual load/store instructions of the SPEC benchmarks are profiled. The profiles show that a small number of instructions contribute to a large percentage of the misses. By scheduling the instructions that miss to hide latency, a factor of three improvement is demonstrated for loop-dominated code. By partially controlling cache replacement using the profile information on data reuse up to a 20% reduction in miss ratio is demonstrated."
Languages and Compilers for Parallel Computing
Author: Lawrence Rauchwerger
language: en
Publisher: Springer Nature
Release Date: 2019-11-19
This book constitutes the proceedings of the 30th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2017, held in College Station, TX, USA, in October 2017. The 17 full papers presented together with abstracts of 5 keynote talks, 11 invited speakers and 4 poster papers in this volume were carefully reviewed and selected from 26 submissions. LCPC encourages submissions that go outside its original scope of scientific computing to diverse areas that are enable or enhanced by the power of parallel systems such as mobile computing, big data, relevant aspects of machine learning, data centers, cognitive computing, etc. LCPC strongly encourages personal interaction and technical discussions along the initial material.
Network and Parallel Computing
Author: Chen Ding
language: en
Publisher: Springer Science & Business Media
Release Date: 2010-08-30
This book constitutes the refereed proceedings of the IFIP International Conference, NPC 2010, held in Zhengzhou, China, in September 2010. The 39 papers presented were carefully selected from 89 submissions. The papers are organized in topical sections on Parallelization and Optimization, Parallel Algorithms, Network, CPU and Multicore, Cloud and Grid Infrastructure, Network on Chip.