Instruction Level Parallel Processors A New Architectural Model For Simulation And Analysis
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Instruction Level Parallel Processors -- a New Architectural Model for Simulation and Analysis
Author: Stanford University. Computer Systems Laboratory
language: en
Publisher:
Release Date: 1994
Trends in high-performance computer architecture have led to the development of increased clock-rate and dynamic multiple-instruction issue processor designs. There have been problems combining both these techniques due to the pressure that the complex scheduling and issue logic puts on the cycle time. This problem has limited the performance of multiple-instruction issue architectures. The alternative approach of static multiple-operation issue avoids the clock-rate problem by allowing the hardware to concurrently issue only those operations that the compiler scheduled to be issued concurrently. Since there is no hardware support required to achieve multiple-operation issue (there are multiple operations in a single instruction and the hardware issues a single instruction at a time), these designs can be effectively scaled to high clock rates. However, these designs have the problem that the scheduling of operations into instructions is rigid and to increase the performance of the system the entire system must be scaled uniformly so that the static schedule is not compromised. This report describes an architectural model that allows a range of hybrid architectures to be studied.
Computer Science Handbook
When you think about how far and fast computer science has progressed in recent years, it's not hard to conclude that a seven-year old handbook may fall a little short of the kind of reference today's computer scientists, software engineers, and IT professionals need. With a broadened scope, more emphasis on applied computing, and more than 70 chap
The Second Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
Author: N. N. Mirenkov
language: en
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
Release Date: 1997
Proceedings -- Parallel Computing.