Implementing Binary Neural Networks
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Implementing Binary Neural Networks
The recent renaissance of deep neural networks has lead to impressive advancements in many domains of machine learning. However, the computational cost of these neural models in- creases in line with their performance, with many state-of-the-art models only being able to run on expensive high-end hardware. The need to efficiently deploy neural networks to commodity platforms has made network optimization a popular field of research. One particularly promising technique is network binarization, which quantizes the weights and activations of a model to only one or two bits. Although binarization offers theoretical oper- ation count reductions of up to 32X, no actual measurements have been reported. This is a symptom of the gap between theory and implementation of binary networks that exists to- day. In this work, we bridge the gap between abstract simulations and real usable high speed networks. To do so, we identify errors in the existing literature, develop novel algorithms, and introduce Riptide, an open source system that can train and deploy state-of-the-art binary neural networks to multiple hardware backends.
Binary Neural Networks
Key Features: Review recent advances in CNN compression and acceleration Elaborate recent advances on binary neural network (BNN) technologies Introduce applications of Binary Neural Network in image classification, speech recognition, object detection etc.
Resistive Random Access Memory (RRAM)
Author: Shimeng Yu
language: en
Publisher: Morgan & Claypool Publishers
Release Date: 2016-03-18
RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM’s potential novel applications beyond the NVM applications.