Ieee Std 1149 1 2001
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The Boundary-Scan Handbook
Aimed at electronics industry professionals, this 4th edition of the Boundary Scan Handbook describes recent changes to the IEEE1149.1 Standard Test Access Port and Boundary-Scan Architecture. This updated edition features new chapters on the possible effects of the changes on the work of the practicing test engineers and the new 1149.8.1 standard. Anyone needing to understand the basics of boundary scan and its practical industrial implementation will need this book. Provides an overview of the recent changes to the 1149.1 standard and the effect of the changes on the work of test engineers; Explains the new IEEE 1149.8.1 subsidiary standard and applications; Describes the latest updates on the supplementary IEEE testing standards. In particular, addresses: IEEE Std 1149.1 Digital Boundary-ScanIEEE Std 1149.4 Analog Boundary-ScanIEEE Std 1149.6 Advanced I/O TestingIEEE Std 1149.8.1 Passive Component TestingIEEE Std 1149.1-2013 The 2013 Revision of 1149.1IEEE Std 1532 In-System ConfigurationIEEE Std 1149.6-2015 The 2015 Revision of 1149.6
Advances in Computer Systems Architecture
Author: Lynn Choi
language: en
Publisher: Springer Science & Business Media
Release Date: 2007-07-30
The refereed proceedings of the 12th Asia-Pacific Computer Systems Architecture Conference are presented in this volume. Twenty-six full papers are presented together with two keynote and eight invited lectures. Collectively, they represent some of the most important developments in computer systems architecture. The papers emphasize hardware and software techniques for state-of-the-art, multi-core and multi-threaded architectures.
Debugging Systems-on-Chip
This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly. Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug flow to be used during the design of an SOC, and customizable off-chip debugger software. Coverage includes an evaluation of the efficiency and effectiveness of the CSAR approach and its supporting infrastructure, using six industrial SOCs and an illustrative, example SOC model. The authors also quantify the hardware cost and design effort to support their approach.