High Speed System And Analog Input Output Design
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High-Speed System and Analog Input/Output Design
The new edition of this textbook is based on Dr. Thanh T. Tran’s 10+ years’ experience teaching high-speed digital and analog design courses at Rice University and 30+ years’ experience working in high-speed system design, including signal and power integrity in digital signal processing (DSP), computer, and embedded system. The book provides hands-on, practical instruction on high-speed digital and analog design for students and working engineers. The author first presents good high-speed digital and analog design practices that minimize both component and system noise and ensure system design success. He then presents guidelines to be used throughout the design process to reduce noise and radiation and to avoid common pitfalls while improving quality and reliability. The book is filled with tips on design and system simulation that minimize late stage redesign costs and product shipment delays. Hands-on design examples focusing on audio, video, analog filters, DDR memory, and power supplies are featured throughout. In addition, the author provides a practical approach to design multi-gigahertz high-speed serial busses (USB-C, PCIe, HDMI, DP) and simulate printed circuit board insertion and return loss using s-parameter models.
Design of High-speed Communication Circuits
MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
High Speed Serdes Devices and Applications
Author: David Robert Stauffer
language: en
Publisher: Springer Science & Business Media
Release Date: 2008-12-19
The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next chip. Once upon a time this was an acceptable approach. However, one aspect (and perhaps the only aspect) of chip design which has not changed during the career of the authors is Moore’s Law, which has dictated substantial increases in the number of circuits that can be manufactured on a chip. The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design. HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10 Gbps and beyond. Chip designers with a background in digital logic design tend to view HSS devices as simply complex digital input/output cells. This view ignores the complexity associated with serially moving billions of bits of data per second. At these data rates, the assumptions associated with digital signals break down and analog factors demand consideration. The chip designer who oversimplifies the problem does so at his or her own peril.