High Speed And High Performance Direct Digital Frequency Synthesizer Design
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High-Speed and High-Performance Direct Digital Frequency Synthesizer Design
The book focuses on design technology of high-speed and high-performance direct digital frequency synthesizer (DDS) chip. The technologies involves phase to amplitude converter design, D/A converter design, phase accumulator design, multi-chip synchronization circuit design, etc. In each chapter, the concept of the technology is explained first, and then the features of different implementation schemes are introduced through the real design cases. More over, a design case of a 2.5GHz monolithic DDS in 0.18 μm CMOS which was designed by the authors are introduced in detail, which can help the reader understanding about the of DDS design deeply. The book is suitable for the readers who are interested to learn practical design technology in DDS. The book can benefit researchers, engineers, and graduate students in fields of mix-signal IC design, communication engineering, electronics engineering, and radar engineering, etc.
Direct Digital Frequency Synthesizers
Author: Venceslav F. Kroupa
language: en
Publisher: John Wiley & Sons
Release Date: 1998-11-18
With the advent of integrated circuits (IC), digital systems havebecome widely used in modern electronic devices, includingcommunications and measurement equipment. Direct Digital FrequencySynthesizers (DDS) are used in communications as transmitterexciters and local oscillators in receivers. The advantages aresuperior frequency stability, the same as that of the driving clockoscillator, and short switching times. The difficulties are loweroutput frequencies and rather large spurious signals. Compiled for practicing engineers who do not have theprerequisite of a specialist's knowledge in Direct DigitalFrequency Synthesizers (DDS), this collection of 40 importantreprinted papers and 9 never-before published contributionspresents a comprehensive introduction to DDS properties and a clearunderstanding of actual devices. The information in this volume canlead to easier computer simulations and improved designs. Featured topics include: * Discussion of principles and state of the art of wide-rangeDDS * Investigation of spurious signals in DDS * Combination of DDS with Phase Lock Loops (PLL) * Examination of phase and background 'noise' in DDS * Introduction to Digital to Analog Conversion (DAC) * Analysis of mathematics of quasiperiodic omission ofpulses DDFS can also serve as a textbook for students seeking essentialbackground theory.
Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters
Author: Ameya Bhide
language: en
Publisher: Linköping University Electronic Press
Release Date: 2015-08-19
Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ?? DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ?? DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ?? DAC architectures, even in nanometer CMOS processes. Time-interleaved ?? (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ?? DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ?? modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ?? DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ?? DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ?? DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ?? DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.