High Performance And Low Power Hardware Implementation For Cryptographic Hash Functions

High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions

Reconfigurable Cryptographic Processor

This book focuses on the design methods for reconfigurable computing processors for cryptographic algorithms. It covers the dynamic reconfiguration analysis of cryptographic algorithms, hardware architecture design, and compilation techniques for reconfigurable cryptographic processors, and also presents a case study of implementing the reconfigurable cryptographic processor “Anole” designed by the authors’ team. Moreover, it features discussions on countermeasures against physical attacks utilizing partially and dynamically reconfigurable array architecture to enhance security, as well as the latest trends for reconfigurable cryptographic processors. This book is intended for research scientists, graduate students, and engineers in electronic science and technology, cryptography, network and information security, as well as computer science and technology.

Proceedings of the IEEE International Symposium on Industrial Electronics