Hardware Design And Simulation In Val Vhdl
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Hardware Design and Simulation in VAL/VHDL
Author: Larry M. Augustin
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
The VHSIC Hardware Description Language (VHDL) provides a standard machine processable notation for describing hardware. VHDL is the result of a collaborative effort between IBM, Intermetrics, and Texas Instruments; sponsored by the Very High Speed Integrated Cir cuits (VHSIC) program office of the Department of Defense, beginning in 1981. Today it is an IEEE standard (1076-1987), and several simulators and other automated support tools for it are available commercially. By providing a standard notation for describing hardware, especially in the early stages of the hardware design process, VHDL is expected to reduce both the time lag and the cost involved in building new systems and upgrading existing ones. VHDL is the result of an evolutionary approach to language devel opment starting with high level hardware description languages existing in 1981. It has a decidedly programming language flavor, resulting both from the orientation of hardware languages of that time, and from a ma jor requirement that VHDL use Ada constructs wherever appropriate. During the 1980's there has been an increasing current of research into high level specification languages for systems, particularly in the software area, and new methods of utilizing specifications in systems de velopment. This activity is worldwide and includes, for example, object oriented design, various rigorous development methods, mathematical verification, and synthesis from high level specifications. VAL (VHDL Annotation Language) is a simple further step in the evolution of hardware description languages in the direction of applying new methods that have developed since VHDL was designed.
Circuit Design and Simulation with VHDL, second edition
A presentation of circuit synthesis and circuit simulation using VHDL (including VHDL 2008), with an emphasis on design examples and laboratory exercises. This text offers a comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits. It focuses on the use of VHDL rather than solely on the language, showing why and how certain types of circuits are inferred from the language constructs and how any of the four simulation categories can be implemented. It makes a rigorous distinction between VHDL for synthesis and VHDL for simulation. The VHDL codes in all design examples are complete, and circuit diagrams, physical synthesis in FPGAs, simulation results, and explanatory comments are included with the designs. The text reviews fundamental concepts of digital electronics and design and includes a series of appendixes that offer tutorials on important design tools including ISE, Quartus II, and ModelSim, as well as descriptions of programmable logic devices in which the designs are implemented, the DE2 development board, standard VHDL packages, and other features. All four VHDL editions (1987, 1993, 2002, and 2008) are covered. This expanded second edition is the first textbook on VHDL to include a detailed analysis of circuit simulation with VHDL testbenches in all four categories (nonautomated, fully automated, functional, and timing simulations), accompanied by complete practical examples. Chapters 1–9 have been updated, with new design examples and new details on such topics as data types and code statements. Chapter 10 is entirely new and deals exclusively with simulation. Chapters 11–17 are also entirely new, presenting extended and advanced designs with theoretical and practical coverage of serial data communications circuits, video circuits, and other topics. There are many more illustrations, and the exercises have been updated and their number more than doubled.
VHDL Designer’s Reference
Author: Jean-Michel Bergé
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • Which modeling methodology should be adopted? • How should the VHDL environment be customized? • What are the tricks? Where are the traps? • What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company.