Graph Reduction

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Graph Reduction

Author: Joseph H. Fasel
language: en
Publisher: Springer Science & Business Media
Release Date: 1987-10-07
This volume describes recent research in graph reduction and related areas of functional and logic programming, as reported at a workshop in 1986. The papers are based on the presentations, and because the final versions were prepared after the workshop, they reflect some of the discussions as well. Some benefits of graph reduction can be found in these papers: - A mathematically elegant denotational semantics - Lazy evaluation, which avoids recomputation and makes programming with infinite data structures (such as streams) possible - A natural tasking model for fine-to-medium grain parallelism. The major topics covered are computational models for graph reduction, implementation of graph reduction on conventional architectures, specialized graph reduction architectures, resource control issues such as control of reduction order and garbage collection, performance modelling and simulation, treatment of arrays, and the relationship of graph reduction to logic programming.
An Architecture for Combinator Graph Reduction

An Architecture for Combinator Graph Reduction examines existing methods of evaluating lazy functional programs using combinator reduction techniques, implementation, and characterization of a means for accomplishing graph reduction on uniprocessors, and analysis of the potential for special-purpose hardware implementations. Comprised of eight chapters, the book begins by providing a background on functional programming languages and existing implementation technology. Subsequent chapters discuss the TIGRE (Threaded Interpretive Graph Reduction Engine) methodology for implementing combinator graph reduction; the TIGRE abstract machine, which is used to implement the graph reduction methodology; the results of performance measurements of TIGRE on a variety of platforms; architectural metrics for TIGRE executing on the MIPS R2000 processor; and the potential for special-purpose hardware to yield further speed improvements. The final chapter summarizes the results of the research, and suggests areas for further investigation. Computer engineers, programmers, and computer scientists will find the book interesting.