Fpga Based Hardware Implementation Of Advanced Encryption Standard
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FPGA Based Hardware Implementation of Advanced Encryption Standard
On October, 2, 2000, The National Institute of Standards and Technology (NIST) announced Rijndael as the new Advanced Encryption Standard (AES). The other competing algorithms were Mars, RC6, Serpent and Two-fish. The Predecessor to the AES was Data Encryption Standard (DES) which is considered to be insecure because of its vulnerability to brute force attacks. DES was a standard from 1977 and stayed until the mid 1990’s. However, by the mid 1990s, it was clear that the DES’s 56-bit key was no longer big enough to prevent attacks mounted on contemporary computers, which were thousands of times more powerful than those available when the DES was standardized. The AES is a 128 bit Symmetric block Cipher. This Thesis provides three different architectures for encrypting/decrypting 128 bit data using the AES. The encryption and decryption modules include the Key Expansion module which generates Key for all iterations on the fly. The first one is the Basic iterative AES, which reuses the same Hardware for all the ten iterations. The second is a one stage sub pipelined AES, which is pipelined, with one stage of outer pipelining in the data block. The above two architectures are synthesized and implemented in Virtex IV FPGA family of devices. These circuits were also tested and verified using CHIPSCOPE pro. The basic iterative AES encryption encodes data at 2.3 Gbps and one stage sub pipelined AES encodes at 5.1 Gbps. Extending the one stage to four stages pipelined AES which is the third architecture, the efficiency increases to 7.2 Gbps. These architectures are compared with the architectures in the Literature.
Proceedings of the International Conference on Intelligent Computing, Communication and Information Security
This book contains high quality research papers accepted and presented at the International Conference on Intelligent Computing, Communication and Information Security (ICICCIS 2022), organized by Swami Keshvanand Institute of Technology, Management & Gramothan (SKIT), Jaipur, India during 25-26, November 2022. It presents the solutions of issues and challenges in intelligent computing, communication and information security domains. This book provides a background to problem domains, considering the progress so far, assessing the potential of such approaches, and exploring possible future directions as a single readily accessible source.
Proceedings of the 12th National Technical Seminar on Unmanned System Technology 2020
This book comprises the proceedings of the 12th National Technical Symposium on Unmanned System Technology 2020 (NUSYS’20) held on October 27–28, 2020. It covers a number of topics, including intelligent robotics, novel sensor technology, control algorithms, acoustics signal processing, imaging techniques, biomimetic robots, green energy sources, and underwater communication backbones and protocols, and it appeals to researchers developing marine technology solutions and policy-makers interested in technologies to facilitate the exploration of coastal and oceanic regions.