Firewire System Architecture
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FireWire System Architecture
Author: Don Anderson
language: en
Publisher: Addison-Wesley Professional
Release Date: 1999
The FireWire (IEEE 1394a) standard for high-speed serial bus communications has come to the fore as an important technology supporting today's emerging data-intensive applications.
FireWire System Architecture
Author: Don Anderson
language: en
Publisher: Addison Wesley Publishing Company
Release Date: 1998
FireWire System Architecture details the various layers and provides transaction examples to explain and illustrate the relationships between each layer. It explores important features of 1394 including: node architecture; address space; arbitration; transaction types: isochronous, asynchronous, lock; broadcast transactions; control and status registers (CSRs); automatic configuration; configuration ROM; bus management; physical layer; transaction layer; link layer; and cable and electrical interface.
ISA System Architecture
Intro to microprocessor communications - Introduction to the bus cycle - Addressing I/0 and memory - The address decode logic - The 80286 microprocessor - The reset logic - The power-up sequence - The 80286 system kernel : the engine - Detailed view of the 80286 bus cycle - The 80386 DX and SX microprocessors - The 80386 system kernel - Detailed view of the 80386 bus cycles - RAM memory : theory of operation - Cache memory concepts - ROM memory - ISA bus structure - Types of ISA bus cycles - The interrupt subsystem - Direct memory access (DMA) - ISA bus masters - RTC and configuration RAM - Keyboard/mouse interface - Numeric coprocessor - ISA timers.