Epitaxial Design Optimizations For Increased Efficiency In Gaas Based High Power Diode Lasers

Epitaxial Design Optimizations for Increased Efficiency in GaAs-Based High Power Diode Lasers

This work presents progress in the root-cause analysis of power saturation mechanisms in continuous wave (CW) driven GaAs-based high-power broad area diode lasers operated at 935 nm. Target is to increase efficiency at high optical CW powers by epitaxial design. The novel extreme triple asymmetric (ETAS) design was developed and patented within this work to equip diode lasers that use an extremely thin p-waveguide with a high modal gain. An iterative variation of diode lasers employing ETAS designs was used to experimentally clarify the impact of modal gain on the temperature dependence of internal differential quantum efficiency (IDQE) and optical loss. High modal gain leads to increased free carrier absorption from the active region. However, less power saturation is observed, which must then be attributed to an improved temperature sensitivity of the IDQE. The effect of longitudinal spatial hole burning (LSHB) leads to above average non-linear carrier loss at the back facet of the device. At high CW currents the junction temperature rises. Therefore, not only the asymmetry of the carrier profile increases but also the average carrier density in order to compensate for the decreased material gain and increased threshold gain. This carrier non-pinning effect above threshold is found in this work to enhance the impact of LSHB already at low currents, leading to rapid degradation of IDQE with temperature. This finding puts LSHB into a new context for CW-driven devices as it emphasizes the importance of low carrier densities at threshold. The carrier density was effectively reduced by applying the novel ETAS design. This enabled diode lasers to be realized that show minimized degradation of IDQE with temperature and therefore improved performance in CW operation.

Epitaxial Design Optimizations for Increased Efficiency in GaAs-Based High Power Diode Lasers

Short channel GaN FET MMIC technology for high reliability applications (Band 74)

Nowdays GaN HEMT technology reached maturity level that allows industral fabrication of such devices for wide range of civil (telecommunications, power electrinics, automotive etc.), as well as space and military (phased array radars) applications. At this level, technology start reaching physical limits of GaN material and require new approaches that will allow to overcome some of well known problems related to GaN HEMTs, such as high gate leakage currents, reliability issues and difficulties of normally-off transistor fabrication. The goal of these theses is theoretical and experimental confirmation of the idea, that using peizoelectric nature of GaN crystal will allow local modification of GaN HEMT channel by means of external mechanical stress (using first and second passivation layers as stressors). After implementation of the proposed technology changes and new device geometry in process flow intended for 150 nm GaN HEMTMMIC fabrication, E/D devices with pinch-off voltages +0.1V and -1.65V respectively were fabricated on the same wafer within single process flow. It was observed, that E-mode devices, fabricated using compressed passivation layers, demonstrate lower gate leakage currents and more robust in HTRB test as compared to D-mode devices. In summary, it was demonstrated, that it is possible to control pinch-off voltage and gate leakage current of short channel GaN HEMTs by application of external stress. Usage of external stress, opens new degree of freedom in device optimization, and extends opportunities for more advanced MMIC design.