Efficient Vlsi Architectures For Error Control Coders

Efficient VLSI Architectures for Error Control Coders

VLSI Architectures for Modern Error-Correcting Codes

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

Error Control Coding for B3G/4G Wireless Systems

Covering the fast evolving area of advanced coding, Error Control Coding for B3G/4G Wireless Systems targets IMT-Advanced systems to present the latest findings and implementation solutions. The book begins by detailing the fundamentals of advanced coding techniques such as Coding, Decoding, Design, and Optimization. It provides not only state-of-the-art research findings in 3D Turbo-codes, non-binary LDPC Codes, Fountain, and Raptor codes, but also insights into their real-world implementation by examining hardware architecture solutions, for example VLSI complexity, FPGA, and ASIC. Furthermore, special attention is paid to Incremental redundancy techniques, which constitute a key feature of Wireless Systems. A promising application of these advanced coding techniques, the Turbo-principle (also known as iterative processing), is illustrated through an in-depth discussion of Turbo-MIMO, Turbo-Equalization, and Turbo-Interleaving techniques. Finally, the book presents the status of major standardization activities currently implementing such techniques, with special interest in 3GPP UMTS, LTE, WiMAX, IEEE 802.11n, DVB-RCS, DVB-S2, and IEEE 802.22. As a result, the book coherently brings together academic and industry vision by providing readers with a uniquely comprehensive view of the whole topic, whilst also giving an understanding of leading-edge techniques. Includes detailed coverage of coding, decoding, design, and optimization approaches for advanced codes Provides up to date research findings from both highly reputed academics and industry standpoints Presents the latest status of standardization activities for Wireless Systems related to advanced coding Describes real-world implementation aspects by giving insights into architecture solutions for both LDPC and Turbo-codes Examines the most advanced and promising concepts of turbo-processing applications: Turbo-MIMO, Turbo-Equalization, Turbo-Interleaving