Developpement D Un Systeme Multiprocesseur Sur Puce Generique Destine Aux Applications Paralleles Et Adaptables Dans Un Environnement Asic

Développement d'un système multiprocesseur sur puce générique destiné aux applications parallèles et adaptables dans un environnement ASIC

Développement d'applications parallèles pour un système multiprocesseur expérimental

Méthodologie de conception automatique pour multiprocesseur sur puce hétérogène

ITRS Semiconductor roadmap projects that hundreds of processors will be needed for future generation multiprocessor system on chip (MPSOC) designs. Current research topics contain modelling of multiprocessors and adequate levels of abstraction (TLM, RTL), performance evaluation and design space exploration, verification and test trough simulation or emulation. Design productivity is one of the most important challenges, which is a relatively new and open research issue. We propose to improve design productivity by raising IP reuse level to small scale multiprocessor (SSM) IP and by combining fast extension techniques for system level design automation in the framework of multi-FPGA emulator. In the thesis, different state-of-art NoC and MPSoC design methodologies are analyzed and compared to better understand the design approaches and to overcome their shortcomings. Then a fully automatic multi-objective design workflow is proposed for network on chip (NoC) at TLM (Transaction Level Modeling) level. The timing and area criteria extracted from RTL level are explored but not limited using the TLM NoC models of NoCexplorer, tool from Arteris. A linear programming methodology is provided as a solution for the organization and dimensioning of eFPGA reconfigurable area to maximize the efficiency of network on chip mapping. The main contribution is the automatic design flow for large scale MPSoC design based on the reuse of SSM IP. Based on it, an automatic design flow is proposed for data parallel and pipelined signal processing applications on multiprocessor with NoC, using cryptographic application TDES (Triple Data Encryption Standard) as an example. High level synthesis tool is used to generate hardware accelerators, which are added to explore the tradeoff in area-performance while still privileging multiprocessor basis for the implementation. OCP-IP NoC benchmarks are executed on the generated 48-core and 672-core multi-processor for performance evaluation. All the work done in this thesis is the basis of “MPSOC explorer”, an ongoing industrial project for large scale MPSoC design exploration supported by European Union and French government.