Design Verification With E
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Design Verification with E
Author: Samir Palnitkar
language: en
Publisher: Prentice Hall Professional
Release Date: 2004
As part of the Modern Semiconductor Design series, this book details a broad range of e-based topics including modelling, constraint-driven test generation, functional coverage and assertion checking.
ASIC/SoC Functional Design Verification
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
Practical Design Verification
Author: Dhiraj K. Pradhan
language: en
Publisher: Cambridge University Press
Release Date: 2009-06-11
Improve design efficiency & reduce costs with this guide to formal & simulation-based functional verification. Presenting a theoretical & practical understanding of the key issues involved, it explains both formal techniques (model checking, equivalence checking) & simulation-based techniques (coverage metrics, test generation).