Design Of Integrated Frequency Synthesizers And Clock Data Recovery For 60 Ghz Wireless Communications
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Design of Integrated Frequency Synthesizers and Clock-data Recovery for 60 GHz Wireless Communications
In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. : The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.
Analog Circuit Design for Communication SOC
Author: Steve Hung-Lung Tu
language: en
Publisher: Bentham Science Publishers
Release Date: 2012
This e-book provides several state-of-the-art analog circuit design techniques. It presents both empirical and theoretical materials for system-on-a-chip (SOC) circuit design. Fundamental communication concepts are used to explain a variety of topics including data conversion (ADC, DAC, S-? oversampling data converters), clock data recovery, phase-locked loops for system timing synthesis, supply voltage regulation, power amplifier design, and mixer design. This is an excellent reference book for both circuit designers and researchers who are interested in the field of design of analog communic.
Proceedings of the International Conference on Systems, Science, Control, Communication, Engineering and Technology 2015
Author: Kokula Krishna Hari K
language: en
Publisher: Association of Scientists, Developers and Faculties (ASDF)
Release Date: 2015-08-10
ICSSCCET 2015 will be the most comprehensive conference focused on the various aspects of advances in Systems, Science, Management, Medical Sciences, Communication, Engineering, Technology, Interdisciplinary Research Theory and Technology. This Conference provides a chance for academic and industry professionals to discuss recent progress in the area of Interdisciplinary Research Theory and Technology. Furthermore, we expect that the conference and its publications will be a trigger for further related research and technology improvements in this important subject. The goal of this conference is to bring together the researchers from academia and industry as well as practitioners to share ideas, problems and solutions relating to the multifaceted aspects of Interdisciplinary Research Theory and Technology.