Design Of High Speed Folding And Interpolating Analog To Digital Converter
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Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter of Embedded Systems
Author: Keh-La Lin
language: en
Publisher: Springer Science & Business Media
Release Date: 2006-01-14
One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.
Design of High Speed Folding and Interpolating Analog-to-digital Converter
High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.
Analog Circuit Design
Author: Rudy J. van de Plassche
language: en
Publisher: Springer Science & Business Media
Release Date: 2013-03-09
Today digital signal processing systems use advanced CMOS technologies requiring the analog-to-digital converter to be implemented in the same (digital) technology. Such an implementation requires special circuit techniques. Furthermore the susceptibility of converters to ground bounce or digital noise is an important design criterion. In this part different converters and conversion techniques are described that are optimized for receiver applications. Part II, Sensor and Actuator Interfaces, interfaces for sensors and actuators shape the gates through which information is acquired from the real world into digital information systems, and vice versa. The interfaces should include analog signal conditioning, analog-to-digital conversion, digital bus interfaces and data-acquisition networks. To simplify the use of data-acquisition systems additional features should be incorporated, like self-test, and calibration