Design And Development Of A Reconfigurable Cryptographic Co Processor
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Design and Development of a Reconfigurable Cryptographic Co-processor
Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more exibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES) . Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the exible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other security circuits.
Reconfigurable Cryptographic Processor
This book focuses on the design methods for reconfigurable computing processors for cryptographic algorithms. It covers the dynamic reconfiguration analysis of cryptographic algorithms, hardware architecture design, and compilation techniques for reconfigurable cryptographic processors, and also presents a case study of implementing the reconfigurable cryptographic processor “Anole” designed by the authors’ team. Moreover, it features discussions on countermeasures against physical attacks utilizing partially and dynamically reconfigurable array architecture to enhance security, as well as the latest trends for reconfigurable cryptographic processors. This book is intended for research scientists, graduate students, and engineers in electronic science and technology, cryptography, network and information security, as well as computer science and technology.
Cryptographic Hardware and Embedded Systems
This book constitutes the refereed proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems, CHES'99, held in Worcester, MA, USA in August 1999. The 27 revised papers presented together with three invited contributions were carefully reviewed and selected from 42 submissions. The papers are organized in sections on cryptographic hardware, hardware architectures, smartcards and embedded systems, arithmetic algorithms, power attacks, true random numbers, cryptographic algorithms on FPGAs, elliptic curve implementations, new cryptographic schemes and modes of operation.