Defect Oriented Testing For Nano Metric Cmos Vlsi Circuits
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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Author: Manoj Sachdev
language: en
Publisher: Springer Science & Business Media
Release Date: 2007-06-04
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Author: Andrei Pavlov
language: en
Publisher: Springer Science & Business Media
Release Date: 2008-06-01
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.