Concurrent And Comparative Discrete Event Simulation

Concurrent and Comparative Discrete Event Simulation

Concurrent simulation is over twenty years old. During that pe riod it has been widely adopted for the simulation of faults in digital circuits, for which it provides a combination of extreme efficiency and generality . Yet, it is remarkable that no book published so far presents a correct and sufficiently detailed treatment of concurrent simulation. A first reason to welcome into print the effort of the authors is, therefore, that it provides a much needed account of an important topic in design automation. This book is, however, unique for sev eral other reasons. It is safe to state that no individual has contrib uted more than Ernst Ulrich to the development of digital logic simulation. For concurrent simulation, one may say that Ernst has contributed more than the rest of the world. We would find such a claim difficult to dispute. The unique experience of the authors con fers a special character to this book: It is authoritative, inspired, and focused on what is conceptually important. Another unique aspect of this book, perhaps the one that will be the most surprising for many readers, is that it is strongly projected towards the future. Concurrent simulation is presented as a general experimentation methodology and new intriguing applications are analyzed. The discussion of multi-domain concurrent simulation-- recent work of Karen Panetta Lentz and Ernst Ulrich---is fascinat ing.

Proceedings of the ... European Test Conference

Digital System Test and Testable Design

This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.