Conception Et Realisation Sur Un Multiprocesseur D Un Simulateur Reparti D Architectures Systoliques

Proceedings of the 2nd European Simulation Congress, Sept. 9-12, 1986, The Park Hotel, Antwerp, Belgium

CONCEPTION ET REALISATION SUR UN MULTIPROCESSEUR D'UN SIMULATEUR REPARTI D'ARCHITECTURES SYSTOLIQUES

CE STIMULATEUR PERMET UNE ANALYSE DETAILLEE DU COMPORTEMENT A L'EXECUTION DES ARCHITECTURES SYSTOLIQUES CLASSIQUES AINSI QU'UNE EVALUATION COMPARATIVE DES PERFORMANCES DE DIVERSES SOLUTIONS ALGORITHMIQUES POUR UN PROBLEME DONNE. LE SIMULATEUR EST REALISE SUR UNE ARCHITECTURE MULTI-MICROPROCESSEUR ORGANISEE SELON UNE TOPOLOGIE MAITRE-ESCLAVE, LES DIFFERENTS PROCESSEURS COMMUNIQUANT ENTRE EUX AU MOYEN D'UN BUS COMMUN. CE CHOIX PERMET UNE SIMULQTION RAPIDE POUR UN COUT RELATIVEMENT FAIBLE. LE LOGICIEL DE SIMULATION A ETE ETUDIE POUR IMITER LE PLUS PRECISEMENT POSSIBLE LE COMPORTEMENT REEL D'UN SYSTEME SYSTOLIQUE TOUT EN OFFRANT A L'UTILISATEUR UN ENVIRONNEMENT CONVIVIAL

Systolic Arrays, Papers Presented at the First INT Workshop on Systolic Arrays, Oxford 2-4 July 1986

This book contains the edited proceedings of the First International Workshop on Systolic Arrays. The workshop was the second in a series on topics in VLSI (the first being on Wafer Scale Integration), and brought together workers in the field of systolic arrays and related SIMD architectures from around the world. The papers in this volume have been selected to cover all major aspects of systolic arrays: design methodologies, simulation and formal synthesis, algorithms and architectures, applications and chip designs, testing and fault tolerance, wavefront arrays and SIMD alternatives. Systolic arrays - along with other parallel computer designs - are becoming important for many applications; there is currently a large research effort being devoted to them and commercial ICs are becoming available. Therefore this book is a very timely introduction to, and summary of, the present state of development. The editors: Dr Will Moore has been involved in research into VLSI architectures, including systolic arrays, for six years and has a special interst in regular arrays, testing, faut tolerance and very large circuits. He initiated the First International Workshop on Wafer Scale Integation in 1985 (Adam Hilger 1986) and is planning events on Hardware Accelerators and Designing for Yield. Andrew McCabe has been involved in integrated circuit design and appliactions for eleven years. For the last six years he has managed a VLSI architectures research and development team and has worked on the design of several systolic array ICs. His current interests include parallel processing, systolic algorithms and architecture, formal designmethods, fault tolerance and wafer scale integration. Dr Roddy Urquhart has worked on the research and development of systolic array architectures for four years. He is currently managing a development programme of high performance Ics for digital signal processing.