Characterization Of Substrate Noise Coupling Its Impacts And Remedies In Rf And Mixed Signal Ics
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Characterization of Substrate Noise Coupling, Its Impacts and Remedies in RF and Mixed-signal ICs
Abstract: Substrate noise coupling in integrated circuits is the process by which interference signals generated by high speed digital blocks cause parasitic currents to flow in the silicon substrate and couple devices in various parts of the circuits on this common substrate. In RFIC the switching noise couples to the sensitive analog circuits through the substrate causing degradation in performance and yield hit. Overcoming substrate coupling is a key issue in successful "system on chip" integration. In this thesis a substrate aware design flow is built, calibrated to silicon and used as part of the design flow to uncover substrate coupling problems in RFICs in the design phase. The flow is used to develop the first comprehensive RF substrate noise isolation design guide to be used by RF designers during the design phase. This will allow designers to optimize the design to maximize noise isolation and protect sensitive blocks from being degraded by substrate noise coupling. Several effects of substrate coupling on circuit performance will be identified and remedies will be given based on the design guide. Three case studies are designed to analyze the substrate coupling problem in RFICs. The case studies are designed to attack the problem from the device, circuit and system levels. On the device level a special emphasis is given to designing on chip inductors as an important device in RFIC. An accurate model is developed for a broadband fit of the inductor scattering parameters. This model is shown to be scalable and is proven to be accurate across various frequency bands and geometries. A special emphasis is put on the design for manufacturing effects that affect the design robustness. A circuit level case study is developed and results are compared to simulations and measurements to highlight the need for such a flow before tapping out to ensure a yielding part. The system level problem studied is a GSM receiver where the research results are directly applied to it as a demonstration vehicle to debug and resolve a system level substrate noise coupling problem that otherwise caused a product to be on the edge of malfunction.
Substrate Noise Coupling in RFICs
Author: Ahmed Helmy
language: en
Publisher: Springer Science & Business Media
Release Date: 2008-03-23
The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors’ knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.
Substrate Noise Coupling in Analog/RF Circuits
This book presents case studies to illustrate that careful modeling of the assembly characteristics and layout details is required to bring simulations and measurements into agreement. Engineers learn how to use a proper combination of isolation structures and circuit techniques to make analog/RF circuits more immune to substrate noise. Topics include substrate noise propagation, passive isolation structures, noise couple in active devices, measuring the coupling mechanisms in analog/RF circuits, prediction of the impact of substrate noise on analog/RF circuits, and noise coupling in analog/RF systems.